Mbed OS Reference
Loading...
Searching...
No Matches
pn512_registers.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2013-2018, ARM Limited, All Rights Reserved
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License"); you may
6 * not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
13 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17/**
18 * \file pn512_registers.h
19 * \copyright Copyright (c) ARM Ltd 2013
20 * \author Donatien Garnier
21 */
22
23#ifndef PN512_REGISTERS_H_
24#define PN512_REGISTERS_H_
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include "stack/nfc_common.h"
31#include "pn512.h"
32
33//Page 0 - Command and Status
34#define PN512_REG_PAGE 0x00 //Selects the register page
35#define PN512_REG_COMMAND 0x01 //Starts and stops command execution
36#define PN512_REG_COMIEN 0x02 //Controls bits to enable and disable the passing of Interrupt Requests
37#define PN512_REG_DIVIEN 0x03 //Controls bits to enable and disable the passing of Interrupt Requests
38#define PN512_REG_COMIRQ 0x04 //Contains Interrupt Request bits
39#define PN512_REG_DIVIRQ 0x05 //Contains Interrupt Request bits
40#define PN512_REG_ERROR 0x06 //Error bits showing the error status of the last command executed
41#define PN512_REG_STATUS1 0x07 //Contains status bits for communication
42#define PN512_REG_STATUS2 0x08 //Contains status bits of the receiver and transmitter
43#define PN512_REG_FIFODATA 0x09 //In- and output of 64 byte FIFO-buffer
44#define PN512_REG_FIFOLEVEL 0x0A //Indicates the number of bytes stored in the FIFO
45#define PN512_REG_WATERLEVEL 0x0B //Defines the level for FIFO under- and overflow warning
46#define PN512_REG_CONTROL 0x0C //Contains miscellaneous Control Registers
47#define PN512_REG_BITFRAMING 0x0D //Adjustments for bit oriented frames
48#define PN512_REG_COLL 0x0E //Bit position of the first bit collision detected on the RF-interface
49
50//Page 1 - Command
51//#define PN512_REG_PAGE 0x10 //Selects the register page
52#define PN512_REG_MODE 0x11 //Defines general modes for transmitting and receiving
53#define PN512_REG_TXMODE 0x12 //Defines the data rate and framing during transmission
54#define PN512_REG_RXMODE 0x13 //Defines the data rate and framing during receiving
55#define PN512_REG_TXCONTROL 0x14 //Controls the logical behavior of the antenna driver pins TX1 and TX2
56#define PN512_REG_TXAUTO 0x15 //Controls the setting of the antenna drivers
57#define PN512_REG_TXSEL 0x16 //Selects the internal sources for the antenna driver
58#define PN512_REG_RXSEL 0x17 //Selects internal receiver settings
59#define PN512_REG_RXTHRESHOLD 0x18 //Selects thresholds for the bit decoder
60#define PN512_REG_DEMOD 0x19 //Defines demodulator settings
61#define PN512_REG_FELNFC1 0x1A //Defines the length of the valid range for the receive package
62#define PN512_REG_FELNFC2 0x1B //Defines the length of the valid range for the receive package
63#define PN512_REG_MIFNFC 0x1C //Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit
64#define PN512_REG_MANUALRCV 0x1D //Allows manual fine tuning of the internal receiver
65#define PN512_REG_TYPEB 0x1E //Configure the ISO/IEC 14443 type B
66#define PN512_REG_SERIALSPEED 0x1F //Selects the speed of the serial UART interface
67
68//Page 2 - CFG
69//#define PN512_REG_PAGE 0x20 //Selects the register page
70#define PN512_REG_CRCRESULT_MSB 0x21 //Shows the actual MSB and LSB values of the CRC calculation
71#define PN512_REG_CRCRESULT_LSB 0x22 //Shows the actual MSB and LSB values of the CRC calculation
72#define PN512_REG_GSNOFF 0x23 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off
73#define PN512_REG_MODWIDTH 0x24 //Controls the setting of the ModWidth
74#define PN512_REG_TXBITPHASE 0x25 //Adjust the TX bit phase at 106 kbit
75#define PN512_REG_RFCFG 0x26 //Configures the receiver gain and RF level
76#define PN512_REG_GSNON 0x27 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation when the drivers are switched on
77#define PN512_REG_CWGSP 0x28 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during times of no modulation
78#define PN512_REG_MODGSP 0x29 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during modulation
79#define PN512_REG_TMODE_TPRESCALERHIGH 0x2A //Defines settings for the internal timer
80#define PN512_REG_TPRESCALERLOW 0x2B //Defines settings for the internal timer
81#define PN512_REG_TRELOADHIGH 0x2C //Describes the 16-bit timer reload value
82#define PN512_REG_TRELOADLOW 0x2D //Describes the 16-bit timer reload value
83#define PN512_REG_TCOUNTERVALHIGH 0x2E //Shows the 16-bit actual timer value
84#define PN512_REG_TCOUNTERVALLOW 0x2F //Shows the 16-bit actual timer value
85
86//Page 3 - TestRegister
87//#define PN512_REG_PAGE 0x30 //Selects the register page
88#define PN512_REG_TESTSEL1 0x31 //General test signal configuration
89#define PN512_REG_TESTSEL2 0x32 //General test signal configuration and PRBS control
90#define PN512_REG_TESTPINEN 0x33 //Enables pin output driver on 8-bit parallel bus (Note: For serial interfaces only)
91#define PN512_REG_TESTPINVALUE 0x34 //Defines the values for the 8-bit parallel bus when it is used as I/O bus
92#define PN512_REG_TESTBUS 0x35 //Shows the status of the internal testbus
93#define PN512_REG_AUTOTEST 0x36 //Controls the digital selftest
94#define PN512_REG_VERSION 0x37 //Shows the version
95#define PN512_REG_ANALOGTEST 0x38 //Controls the pins AUX1 and AUX2
96#define PN512_REG_TESTDAC1 0x39 //Defines the test value for the TestDAC1
97#define PN512_REG_TESTDAC2 0x3A //Defines the test value for the TestDAC2
98#define PN512_REG_TESTADC 0x3B //Shows the actual value of ADC I and Q
99
100
101void pn512_registers_init(pn512_t *pPN512);
102void pn512_registers_reset(pn512_t *pPN512);
103
104void pn512_register_write(pn512_t *pPN512, uint8_t address, uint8_t data);
105uint8_t pn512_register_read(pn512_t *pPN512, uint8_t address);
106
107void pn512_register_switch_page(pn512_t *pPN512, uint8_t address);
108
109#ifdef __cplusplus
110}
111#endif
112
113#endif /* PN512_REGISTERS_H_ */
Definition: pn512.h:53